Study Examines Parallelism Effects on Correlation Power Analysis in Vector Multiplication Units

Global: Influence of Parallelism in Vector-Multiplication Units on Correlation Power Analysis

Researchers Manuel Brosch, Matthias Probst, Stefan Kögler, and Georg Sigl submitted a paper to arXiv on January 9, 2026, investigating how parallel processing within neural‑network accelerators influences correlation‑based side‑channel attacks that target power consumption. The work focuses on fully‑connected layer neurons that execute multiply‑and‑accumulate operations simultaneously, aiming to clarify why increasing parallelism may affect the success rate of correlation power analysis.

Edge Device Security Context

Edge devices are increasingly deploying neural‑network models for inference, exposing confidential model parameters to potential adversaries. Because these devices often permit physical access, attackers can employ hardware‑level techniques such as side‑channel analysis to extract sensitive information, prompting a need for systematic security evaluation.

Parallel Processing in Neural Accelerators

To meet performance demands, hardware accelerators implement vector‑multiplication units that execute multiple multiply‑and‑accumulate operations in parallel. While this parallelism improves throughput, it also alters the aggregate power profile, which could either mask or amplify the leakage exploited by correlation power analysis.

Research Approach

The authors first develop a theoretical model that predicts how concurrent operations influence overall power consumption. They then derive equations describing the expected decline in correlation strength as the number of parallel neurons grows. To validate the model, a vector‑multiplication unit was instantiated on a field‑programmable gate array (FPGA) and subjected to empirical correlation power analysis experiments.

Key Findings

Experimental results confirm that correlation coefficients diminish predictably with higher parallelism levels, reducing the attack’s success probability. The derived equations accurately capture this trend, offering a quantitative tool for estimating side‑channel vulnerability based on architectural parallelism.

Implications for Designers

Designers of neural‑network accelerators can use the presented models to assess trade‑offs between performance gains and side‑channel risk. By selecting appropriate parallelism configurations, they may mitigate leakage without sacrificing computational efficiency.

Future Directions

The study suggests extending the analysis to other layer types, such as convolutional layers, and exploring additional side‑channel modalities like electromagnetic emissions. Further research could also examine countermeasures that intentionally introduce noise to obscure power signatures.

This report is based on information from arXiv, licensed under Academic Preprint / Open Access. Based on the abstract of the research paper. Full text available via ArXiv.