Secure Number Theoretic Transform Architecture Detects Hardware Trojans and Side-Channel Attacks

Global: Secure NTT Architecture Detects Hardware Trojans and Side-Channel Attacks

Researchers have introduced a new Number Theoretic Transform (NTT) design that can identify and mitigate both hardware Trojan‑induced control‑flow disruptions and soft analytical side‑channel attacks (SASCA) in lattice‑based post‑quantum cryptography implementations. The prototype, evaluated on an Artix‑7 FPGA using multiple Kyber algorithm variants, demonstrates high fault‑detection success while incurring limited area and timing penalties.

Background

The NTT is a cornerstone operation for polynomial multiplication in leading post‑quantum schemes such as Kyber, Dilithium, and NTRU. Efficient hardware implementations are essential for meeting performance targets in emerging cryptographic accelerators.

Threat Landscape

Side‑channel attacks and hardware Trojans represent two prominent vectors for compromising the integrity of NTT circuits. While data‑bit faults typically cause localized errors, malicious manipulation of control signals can halt or bypass entire computation sequences, making them especially attractive to adversaries.

Proposed Secure NTT Architecture

The authors describe a suite of detection mechanisms that monitor unconventional timing delays and unexpected control‑flow transitions. An adaptive fault‑correction module is integrated to address identified anomalies, and the design includes safeguards against SASCA by obscuring analytical side‑channel leakage.

Experimental Evaluation

Implementation on a Xilinx Artix‑7 platform involved synthesizing the secure NTT alongside standard counterparts for Kyber‑512, Kyber‑768, and Kyber‑1024. Simulations injected both accidental and intentional faults, including those mimicking hardware Trojan behavior.

Performance and Overhead

Results indicate that the detection and correction circuitry successfully identified and rectified the majority of injected faults, achieving a success rate exceeding 95 %. The additional logic contributed an area increase of approximately 12 % and a latency overhead of roughly 3 % relative to the baseline design.

Implications for Post‑Quantum Hardware

By providing on‑chip verification of NTT operations, the proposed architecture enhances the resilience of PQC accelerators against both malicious hardware modifications and sophisticated side‑channel techniques, addressing a critical security gap in the deployment of quantum‑resistant cryptography.

Future Directions

The study suggests extending the detection framework to other core primitives in lattice‑based schemes and exploring automated synthesis flows that incorporate security checks early in the hardware design process.

This report is based on information from arXiv, licensed under Academic Preprint / Open Access. Based on the abstract of the research paper. Full text available via ArXiv.